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A Circuit Approach for CMOS VLSI Circuit Leakage Power Reduction

Prajyant Pathak, Sateesh Kourav


Despite the fact that scaling CMOS technology boosted speed, leakage currents always remained an issue. The issue has gotten worse as the scaling has gone into the UDSM (ultra-deep-submicron) range. In order for the circuit to function effectively, these unwanted leakage currents must be reduced to a minimum. It is challenging to create these leakage-free nano-scale CMOS circuits. In this work, the issue of leakage power is addressed, which occurs when device channel lengths fall below 100 nm. We propose a circuit technique for reducing device leakage currents by adjusting the voltage at the MOSFET source terminus. The suggested solution decreases the CMOS inverter’s static and total power dissipation by 98% and 30%, respectively. According to simulation studies, employing the same technique, NAND and NOR gates achieved total power improvements of 15.90% and 18.88% over traditional designs, respectively. The proposed method is investigated, and simulation results of an 11-stage CMOS ring oscillator are given Circuits constructed in the manner described yield PDP (Power-Delay Products).


Precision agriculture, technologies involved, chip density, leakage power, low-power design, dual threshold, sleepy approach, variable threshold

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