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Analysis of High Performance 6-Stage 64-Bit MIPS RISC Pipelined Processor Using FPGA VHDL

Sateesh Kourav, Sunil Shah


The powerful 6-stage 64-bit MIPS RISC processor improves the speed and importance of the pipeline process. This is done for 64 steps, six steps in high detail, better for high speed and advanced technology. In a comparative study, our proposed architecture has reduced and increased power by 12% speed compared to our nearest counterpart. Simulation result Xilinx are done with proven the superiority of the platform and our model. Pipelining is a technique that exploits parallelism, to achieve increased throughput between instructions in a sequential instruction stream, and that reduces the total time to complete a job. The main objective of this architecture is to create a low-power highperformance structure that meets all the design requirements. Important factors like power, frequency, area, propagation delay are analyzed using Xilinx tools. The basic functional blocks of a processor include input/output blocks, configurable logic blocks, block RAM, and a digital clock manager, and each block allows multiple sources to be connected for routing. Auxiliary units increase the performance of the processor. The comparative study nullifies the designed model in terms of area, power and frequency.


ALU, VHDL, control unit VLSI, MIPS, RISC

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Pranjali S. Kelgaonkar, Shilpa Kodgire, Design of 32 Bit MIPS RISC Processor Based on Soc, Int J Latest Trends in Eng Technol (IJLTET). January 2016.

Preetam Bhosle, Hari Krishna Moorth, FPGA Implementation of low power pipeline 32-bit RISC Proessor, Int J Innovative Technol Exploring Eng (IJITEE). August 2014.

Ramandeep Kaur, Anuj, 8 Bit RISC Processor Using Verilog HDL, Int J Eng Res Appl. March 2014.

Whytney J. Townsend, Earl E. Swartzlander Jr, Jacob A. Abraham, A Comparison of Dadda and Wallace multiplier delays, Advanced Signal Processing Algorithms, Architectures, and Implementations XIII, SPIE, San Diego, CA, August-2003, 552–560p.

Gautham P, Parthasarathy R, Karthi, Balasubramanian, Low Power Pipelined MIPS Processor Design, in the proceedings of the 2009, 12th international symposium, 2009, 462–465p.

Neenu Joseph, Sabarinath S, FPGA based Implementation of High Performance Architectural level Low Power 32-bit RISC Core, 2009 IEEE.

Barry Fagin, Cyril Renard, Field Programmable Gate Arrays and Floating Point Arithmetic, IEEE Trans Very Large Scale Integration (VLSI) Syst. September 1994; 2(3): 365–367p.

Loucas Louca, Todd A. Cook, William H. Johnson, Implementation of IEEE Single Precision Floating Point Addition and Multiplication on FPGAs, Proceedings of 83 the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM‟96), 1996, 107–116p.

Nabeel Shirazi, Al Walters, Peter Athanas, Quantitative Analysis of Floating Point Arithmetic on FPGA Based Custom Computing Machines, IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, CA, April 1995, 155–162p.

Allan Jaenicke, Wayne Luk, Parameterised Floating-Point Arithmetic on FPGAs, IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP‟01), Salt Lake City, UT, May 2001; 2: 897–900p.

Kelly Liew Suet Swee, Lo Hai Hiung, Performance Comparison Review of 32-bit Multiplier Designs, 4th International Conference on Intelligent and Advanced System (ICIAS), Kuala Lumpur, June 2012; 2: 836–841p.

Suchitha Kamble, Mhala NN. VHDL Implementation of ALU, IOSRJECE. May-June 2012; 1(1).

Linder M, Schmid M. Processor Implementation in VHDL, Project Report-2007, University of ULSTER AT Jordanstown.

Muhammad Aizuddin Bin Che Soh, Design of 8 BIT CPU Implemented on FPGA, Project Report-April 2007, Universiti Teknikal Malaysia Melaka.



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