Designing and Analysis of a Negative Bias Temperature Instability Sensing Circuit

Authors

  • Deepjyoti Kalita
  • Partha Pratim Saikia
  • Debaprasad Das

DOI:

https://doi.org/10.37591/rrjoesa.v8i1.652

Abstract

Scale down the size of devices introduce the effect of negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), and hot carrier injection (HCI) in very-large-scale integration (VLSI) chip design and the major concern is to minimize these effects to a nominal value. In the paper, authors focus in minimization of NBTI effect and develop a noble degradation monitoring sensor circuit named SCHIMOS. A comparison is stated between an analytically strong equisensitive LISOCHIN sensor and SCHIMOS in 90nm and 45nm technology node. Paper experimentally reduces the NBTI effect that is controlled by a number of factors including a reduction in PMOS size, duty cycle, and VDD-Vth tuning. However, NBTI effect degrades the speed and increases the threshold voltage of PMOS transistors.

Keywords: NBTI, SCHIMOS, LISOCHIN, PMOS size, VDD-Vth tuning.

Cite this Article: Deepjyoti Kalita, Partha Pratim Saikia, Debaprasad Das. Designing and Analysis of a Negative Bias Temperature Instability Sensing Circuit. Research & Reviews: A Journal of Embedded System & Applications. 2020; 8(1): 6–11p.

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Published

2020-06-03

Issue

Vol. 8 No. 1 (2020)

Section

Articles

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