Hardware and Power Efficient Single Bit Full Adder Using GDI and PTL Technique

Authors

  • Radhika P
  • Jyothisree K R

Abstract

Abstract: This study presents hardware and power efficient single bit full adder which consists of two techniques, Pass Transistor Logic (PTL) and Gate Diffusion Technique (GDI). Several logic families are described by PTL which is utilized in the architecture of integrated circuits. PTL technique is used to decrease the number of transistors in the circuits to make different logic gates. GDI technique is utilized for the low power consumption. CADENCE VIRTUOSO tool is being used.

Keywords: CADENCE VIRTUOSO tool, CMOS (Complementary Metal Oxide Semiconductor), full adder, Gate Diffusion Input (GDI) technique, Pass Transistor Logic (PTL)

Cite this Article: Radhika P, Jyothisree KR. Hardware and Power Efficient Single Bit Full Adder Using GDI and PTL Technique. Research & Reviews: A Journal of Embedded System & Applications. 2019; 7(3): 9–17p.

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Published

2019-12-31

Issue

Vol. 7 No. 3 (2019)

Section

Articles

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