Design of a Modified Low Power PTL based 64-Bit Comparator

Authors

  • Shilparani Panda
  • Manas Ranjan Jena Department of ELTCE, VSSUT, Burla, Odisha, India
  • Snigdharani Nath Department of ETC, SIET, Dhenkanal,Odisha, India

Keywords:

Binary comparator, digital arithmetic, power delay product, PTL, power, area

Abstract

In this paper, we have presented comparison of modified and existing 64-bit binary comparator designs concentrating on power consumption, delay and PDP. Modifications are done in existing 64-bit binary comparator design to improve the PDP of the proposed design. The modified design have been performed by using PTL logic in existing 64-bit binary comparator design to improve the speed of the circuit. Comparison between modified and existing 64-bit binary comparator designs is calculated by simulation that is performed at 180 nm technology in Tanner EDA Tool.

 

Keywords: Binary comparator, digital arithmetic, power delay product, PTL, power, area

Published

2015-01-06

Issue

Vol. 2 No. 3 (2014)

Section

Articles

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