FPGA Implementation of SoC Design using Softcore Processor and Custom Peripherals, Custom Instruction for Robotics and Automation

Abstract

The general definition of SoC is the on-chip integration of a variety of functional h/w blocks to suite a specific product application. In traditional technology designed using on board integration of functional blocks for any application, this leads to less performance. Nowadays productivity gap will be reduce by making compact, life of device and Time to market. So using FPGA demonstrating building of SoC using custom peripherals. FPGA (Field Programmable Gate Array) devices are particularly suitable for parallel algorithms implementation. Soft CPU cores are usually used to create an FPGA-based system-on-chip (SoC). In this case a CPU core controls the work of the circuit and does some random calculations, and the other parts of the circuit are responsible for interfacing and parallel processing. Nios II is the soft-core 32 bit RISC processor by Altera Corporation which can be implemented in a FPGA. Users can design their own peripherals accord with Avalon Bus specification in Nios II system. Avalon bus is a proprietary bus from Altera. A new design methodology for implementation of pulse width module (PWM) and I2C peripheral is presented, which is coded in Verilog HDL. Accelerate time-critical software algorithms by adding custom instructions to the Nios II instruction set. Designing floating point custom Instruction and executing in hardware and software tools. Comparing and concluding hardware execution instruction takes less clock cycles. Nios II system is used successfully in FPGA, and the CPU's runtime can be saved effectively.