Low-power, High-speed, Full-swing Hybrid Full Adder

Abstract

Abstract: Nowadays VLSI design demands low area and low-power consumption. In this study, a low-power, high-speed, full-swing 1-bit hybrid full adder is proposed. The hybrid full adder is decomposed into three sub-modules. For each sub-module, designs are different. Module 1 and 2 are designed using pass transistor logic (PTL) and Module 3 uses transmission gates to produce carry signal. Then by proposed low-power, high-speed hybrid full adder circuits play a vital role in complex ALUs and DSPs, where power, speed and area are the major constrains. By realizing low-power area efficient hybrid full adder, optimized complex circuits were achieved. The proposed circuit is designed using CADENCE EDA tool and simulated using specter virtuoso.

Keywords: Hybrid full adder, PTL, transmission gates, low power, CADENCE (tool)

Cite this Article: Riya Sara Joy, Simi P. Thomas. Low-power, High-speed, Full-swing Hybrid Full Adder. Research & Reviews: A Journal of Embedded System & Applications. 2019; 7(3): 22–29p.