Design and Simulation of FIR Filter using VHDL

Abstract

Digital Signal Processing (DSP) has gained great popularity in the recent years. DSP is used in the field of communication, medicine and entertainment. Earlier the digital signals use is expensive in the communication devices. DSP makes use of the digital filters in the communication equipment. The basic building block of the digital filter-adder, coefficient multipliers and delays. Digital filter can be implemented efficiently by selecting an efficient representation for filter coefficient. Finite Impulse Response (FIR) filter is the important part in the high speed digital processing and video processing. The research work mainly focuses on the FIR filter design and its implementation on Field Programmable Gate Array (FPGA) In out design, the filter takes x(n) and w(n) inputs of length 4 each and gives y (n) as outputs for the x (n) inputs of coefficient of order 4. A 7-tap filter is designed using the x (n) and w (n) as the input where w (n) is the delayed input to the filter. The output generated is generally a convolution sum of x (n) and w (n). For the designing of an optimum filter area, frequency, speed of operation and hardware requirement are the main aspects to focus. The implementation of the 7-tap FIR filter is done using the Xilinx software using the VHDL language.

Keywords- Digital Signal Processing (DSP), Finite Impulse Response (FIR) filter, Field Programmable Gate Array (FPGA), Very High Speed Integrated Circuit Hardware Description Language (VHDL)