Scrutinizing and Extract the cause of Scaling Concerns for Fin-FET

Authors

  • Vivek Daiya

Abstract

Abstract

Recent Trend in the adaption of New Technological Innovations suggests that People are looking for Power in compactly sized alternatives which suggest that Devices are shrinking down day by day. With increasing demands of Power to Body ratio, it is becoming difficult for the Researchers to cope up with this current scenario. Fin-FET seems to be a possible alternative to combat these expectations but with every new invention comes its flaws. Scaling down the Fin-FET size brings new challenges to the plate. This Paper reviews some of those common issues and later proposes their possible solutions to overcome them. 

Keywords: Fin-FET, Fin-Shape, Parasitic Capacitance, SCE

Cite this Article

Vivek Daiya. Scrutinizing and Extract the cause of Scaling Concerns for Fin-FET. Journal of Communication Engineering & Systems. 2019; 9(3): 8–11p.



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Published

2019-11-14

Issue

Vol. 9 No. 3 (2019)

Section

Articles

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